میکروکنترلر STM32H7B0VBT6

میکرو کنترلر STM32H7B0VBT6 اورجینال و دارای گارانتی

Features

Core

• 32-bit Arm® Cortex®-M7 processor with double-precision FPU and L1 cache
  (16 KB instruction cache + 16 KB data cache).

• Single-access 128-bit flash interface capable of filling one cache line at a time.

• Operating frequency up to 280 MHz.

• Includes MPU, DSP instructions, and delivers 599 DMIPS / 2.14 DMIPS/MHz (Dhrystone 2.1).

Memories

• 128 KB flash memory + 1 KB OTP.

• Approximately 1.4 MB RAM:

  • 192 KB TCM RAM (64 KB ITCM + 128 KB DTCM) for time-critical code,

  • 1.18 MB user SRAM,

  • 4 KB backup SRAM.

• Dual Octo-SPI interfaces with on-the-fly decryption, I/O multiplexing, and support for serial PSRAM/NOR and HyperRAM/HyperFlash (up to 140 MHz SRD mode / 110 MHz DTR mode).

• Flexible external memory controller with up to 32-bit data bus supporting:

  • SRAM, PSRAM, NOR flash (up to 125 MHz synchronous),

  • SDRAM/LPSDR SDRAM,

  • 8/16-bit NAND flash.

• CRC calculation unit.

Security

• ROP, PC-ROP, active tamper detection, secure firmware upgrade support, secure access mode.

GPIO

• Up to 138 interrupt-capable I/O pins.

• Fast I/Os up to 133 MHz.

• Up to 164 pins with 5-V tolerance (package-dependent).

Low-Power Modes

• Stop mode down to 32 µA with full RAM retention.

• Standby mode: 2.8 µA (backup SRAM OFF, RTC/LSE ON, PDR OFF).

• VBAT mode: 0.8 µA (RTC/LSE ON).

Clock System

• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI.

• External oscillators: 4–50 MHz HSE, 32.768 kHz LSE.

• Three PLLs (one system, two peripheral) with fractional mode.

Reset and Power Management

• Two independent power domains for improved power efficiency:

  • CPU domain (Cortex-M7 + peripherals) with retention mode,

  • Smart-Run domain (SRD) for RCC, PMU and selected peripherals.

• 1.62–3.6 V supply range.

• POR, PDR, PVD, BOR.

• Dedicated USB power with internal 3.3 V regulator.

• Dedicated SDMMC power domain.

• Integrated high-efficiency SMPS step-down converter powering VCORE or external loads.

• Integrated LDO with scalable output voltage.

• Voltage scaling support in Run/Stop modes.

• Backup regulator (~0.9 V).

• Low-power modes: Sleep, Stop, Standby.

• VBAT mode with battery-charging capability.

• Power-state monitoring pins.

Interconnect

• Three bus matrices (1× AXI, 2× AHB).

• Bridges: 5× AHB-to-APB, 3× AXI-to-AHB.

DMA

• Total of five DMA controllers:

  • 1× high-speed MDMA,

  • 2× dual-port DMA with FIFO and request routing,

  • 1× basic DMA with routing,

  • 1× DFSDM-dedicated DMA.

Communication Interfaces (up to 35)

• 4× I²C FM+ (SMBus/PMBus).

• 5× USART + 5× UART (ISO7816, LIN, IrDA, modem control) + 1× LPUART.

• 6× SPI (4 supporting full-duplex I²S with audio-class accuracy).

• 2× SAI audio interfaces.

• SPDIFRX.

• SWPMI single-wire master.

• MDIO slave.

• 2× SD/SDIO/MMC (up to 133 MHz).

• 2× CAN FD + 1× TT-CAN.

• USB OTG (HS/FS).

• HDMI-CEC.

• 8–14-bit DCMI camera interface (up to 80 MHz).

• 8/16-bit PSSI parallel interface.

Analog (11 Peripherals)

• 2× ADC, up to 16-bit resolution, 24 channels, 3.6 MSPS.

• Temperature sensors (analog + digital).

• 12-bit single-channel DAC (SRD domain) + 12-bit dual-channel DAC.

• 2× low-power comparators.

• 2× operational amplifiers (8 MHz BW).

• 2× DFSDM blocks (one 8-channel / 8-filter, one 2-channel / 1-filter in SRD).

Graphics

• LCD-TFT controller up to XGA resolution.

• Chrom-ART Accelerator (DMA2D).

• Hardware JPEG codec.

• Chrom-GRC™ (GFXMMU).

Timers and Watchdogs

• 2× 32-bit timers (IC/OC/PWM, pulse counter, quadrature encoder).

• 2× 16-bit advanced motor-control timers.

• 10× 16-bit general-purpose timers.

• 3× low-power 16-bit timers.

• Independent and window watchdogs.

• SysTick timer.

• RTC with sub-second accuracy and full calendar.

Cryptography

• AES modes: ECB, CBC, CTR, GCM, CCM (128/192/256-bit keys).

• HASH: MD5, SHA-1, SHA-2; HMAC support.

• 2× OTFDEC AES-128 engines for Octo-SPI.

• 32-bit TRNG compliant with NIST SP 800-90B.

Debug

• SWD and JTAG.

• 4 KB Embedded Trace Buffer.

• 96-bit unique ID.